This invention relates, in general, to an apparatus and a method for plating metals, and more particularly, to an apparatus and method of plating interconnects on electronic products.
The plating process involves an electrochemical process where a layer of metal is deposited on a surface by creating a voltage potential between the surface to be deposited on and the electrode. In the electronics industry, this plating apparatus and method is used to plate a metallic layer on a portion of a semiconductor wafer to form interconnections, wire bond sites, flip chip bond sites, or tape automated bond sites.
The plating systems used in the past had the problem of indeterminate control of the charging and discharging characteristics of the electrochemical diffusion layer which resulted in nonuniform deposit characteristics across a wafer and nonplanar bump deposits. FIG. 1 depicts, using a scanning electron micrograph, such a plated bump deposit using prior manufacturing methods.
In the past, nonuniform deposits formed were formed because prior art plating systems could not operate at higher frequencies and higher currents required to minimize ion depletion of the diffusion layer. Another problem with the prior art was imprecise control of the plating parameters with regard to the control of voltage and current forcing modes, and the precision and bandwidth of the programmed duty cycle and frequency response. Additionally, prior systems were not capable of maintaining consistent peak operating current profiles at the required higher pulse plating frequencies that are needed during a plating solution's effective manufacturing lifetime.
Prior art methods rely upon operational amplifiers to sense current demands over a period of time that is relatively long compared to the length of a pulse period. The prior art's operational amplifiers are configured as a integrator circuit that has an integration time constant of approximately 20 seconds. This means that an instantaneous change in current demand for a short period of time cannot be responded to very fast. The prior art's operational amplifier integrator circuit's output is tied into the gate of a MOSFET voltage controlled device. The MOSFET acts as a current regulator, in that as the gate voltage is increased, the MOSFET is biased "on" more, and this action allows more current to flow into the electrochemical reaction cell through the bridge circuit. This gate voltage is what takes so long to be affected by the operation amplifier integrator circuit.
The net effect of the prior art's circuit is that it's ability to charge the electrical reactance of the electrochemical diffusion layer on the object to be plated (essentially a paralleled capacitor and resistor) is limited with increasing frequency. As the frequency increases past about 30 Hz, the electrochemical time constant of the diffusion layer overrides the ability of the prior art's circuit to charge the electrochemical diffusion layer. Because the amount of charge transfer is limited to the electrochemical diffusion layer on the rising and falling edges of the prior art's circuitry in both voltage and current control modes, but primarily in voltage control mode, the results of using the prior art equipment cause inconsistent and unpredictable metal deposits to form.
In particular to the electronics industry, the problems described above, in addition to other problems of the systems used in the past, resulted in intolerable process variation of the metal deposition thickness, planarity, grain structure and deposit hardness from wafer to wafer and between interconnection bond sites within a wafer. As can be seen, a system for providing an enhanced level of control of the electrochemical process and optimization of the resulting metal deposition is needed.